S50 TEST SYSTEM | IC Tester | Semiconductor

The Superlative 50MHz Tester

S50 TEST SYSTEM

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S50 TEST SYSTEM
S50 TEST SYSTEM

KEY FEATURES

 
  • 64 to 256 Logic I/O pins - with 64 pin increments 
  • Up to 32 sites parallel testing - simultaneous of up to 32 DUTs, any pin, any resource can be assigned to any site
  • Logic / Mixed-Signal / Analog Options
  • Cable Mount Solution

FUNCTIONS

 

Logic & APG Board
 
  • 50MHz
  • TG and Levels Per Pin, 64 Logic I/O pins
  • 32 Timing Set and 32 Format Set change on-the-fly
  • 16X, 16Y, 16D Algorithmic Pattern Generation
  • +11V/-2V, 35mA driving capability
  • 2 DPS, 8 PMU, 64 PPMU, TMU, DVM
  • 17M local memory

Mixed-Signal Board
 
  • +40V, -15V / ± 1.8A V/I Source/Meter x8
  • 500KSPS / 16 Bits AWG / Digitizer
  • RMS, DVM , TMU , Data Acquisition Unit,
  • 32 User Relay

OPM Board
 
  • 64 Channels, Force and Sense Per Channel
  • +40V, -15V / ± 1.8A V/I Source / Meter x8
  • 4 DVM ,TMU, 32 User Relay
 

APPLICATIONS

 
  • Application specific test solution 
  • Test configurable solution
  • Low cost test solution
  • Mass production proven solution



 

Road Map






 

Download

Title Download
S50 Datasheet
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